Field Effect Transistor technology is a relatively highly developed art, which is currently under extensive development and investigation by the art in general. There are a sizeable number of published articles, patents and text books directed to theory, structure, methods of fabrication, process technology, circuitry and application of field effect devices.
MOSFETs (Metal-Oxide Silicon Field Effect Transistors), MISFETs (Metal Insulator Silicon Field Effect Transistors) and IGFETs (Insulated Gate Field Effect Transistors) are terms extensively employed in the art and possessing well established definitions in the art. "N-channel", "P-channel", "Enhancement Mode", "Depletion Mode" and "CMOS" (Complementary Metal Oxide Silicon) are additional terms extensively employed in the art and possessing well established definitions. and MC1least certain of the foregoing terms will be used hereinafter. When used hereinafter, their use will be in full accord with the generally established definition given said phrase or word in the art.
Numerous texts fully explain the theory of operation of field effect transistors. Two such texts are: (1) "MOSFET in Circuit Design" by Robert H. Crawford (Texas Instrument Series) McGraw Hill, copyright 1967 by Texas Instruments Incorporated and (2) "ELECTRONICS: BJTs, FETs and Microcircuits" by E. James Angelo, Jr., McGraw Hill Electrical and Electronic Engineering Series, copyrighted 1969 by McGraw Hill.
A publication tracing the development of the field effect transistor, evidencing its high state of development, and explaining in non-mathematical terms its operation is the following article: "Metal-Oxide Semiconductor Technology" by William C. Hittinger, Scientific American, August 1973, pages 48 through 57.
U.S. Pat. No. 3,588,846 granted June 28, 1971 to Richard H. Linton is directed to a "Storage Cell With Variable Power Level". The storage cell has two cross coupled FET's which function as the storage element of the cell. The cross coupled FET's are address powered through input/output FET's when the cell is interrogated for reading. When the cell is not being so interrogated, the cross coupled FET's are supplied power from a source which is connected to each of the cross coupled FET's by a separate load FET. The gates of those load FET's are biased so the load FET's supply charge to the cross coupled FET's while the storage cell is not being interrogated but draw charge from the cross coupled FET's when the cross coupled FET's are addressed for reading. By biasing the load FET's in this manner, the potential on the drain can be reduced so as to reduce the overall power dissipation of the storage cell.
U.S. Pat. No. 3,593,037 granted July 13, 1971 to Marcian E. Hoff, Jr. is directed to "Cell For MOS Random-Access Integrated Circuit Memory." The cell is a dynamic storage device which utilizes the parasitic capacitance associated with the lead and gate of an MOS device for storage. The cell is adaptable for use in a memory which has a separate select-write line, select-read line, write data line and read data line.
U.S. Pat. No. 3,683,206 granted Aug. 8, 1972 to Tegze Harasziti is directed to an electrical storage element comprising two controllable elements, such as field effect transistors, controllable into conducting or cut off positions in phase opposition and in dependence on the state of charge of storage capacitances.
Reference is made to U.S. Pat. No. 3,740,732 granted June 19, 1973 to Pierre M. Frandon and directed to a "Dynamic Data Storage Cell". The dynamic data storage cell disclosed in U.S. Pat. No. 3,740,732 requires only one insulated field effect transistor to store binary data. The drain of the FET is connected to a data input line and data is stored at the source node of the transistor by inherent capacitance between the source diffusion and the substrate. The capacitance of the source electrode is enhanced by forming a heavily doped layer to underlie a portion of the source diffusion. Using the substrate as circuit ground enables the fabrication of an array of transistors for a random access memory wherein the surface area of the semiconductor chip is minimized.
U.S. Pat. No. 3,745,539 granted July 10, 1973 to Evan E. Davidson et al is directed to a semiconductor device circuit for reading an FET capacitor store dynamic memory cell and for regenerating the charge (if any) in said capacitor whereby non-destructive read-out is achieved. The memory cell includes an FET switch for selectively connecting the storage capacitor to a memory array bit-sense line through either one of a pair of oppositely connected bi-polar transistors for reading and writing, respectively. The bit sense line is connected to the input terminal of a latching regenerative feedback amplifier such as a silicon controlled rectifier. The potential level at said input terminal rises to a relatively higher level by regenerative feedback action in response to a relatively lower bit-sensing voltage which initiates the latching action. The storage capacitor of the memory cell is recharged via one of the bipolar transistors in response to the aforesaid relatively higher potential at the amplifier input terminal. Bipolar current switch embodiments as well as a silicon controlled rectifier embodiment are disclosed for implementing the latching regenerative feedback amplifier.
U.S. Pat. No. 3,748,498 granted July 24, 1973 to Kurt Hoffman is directed to a quasi-static flip-flop circuit wherein a pair of cross-connected transistors are connected between a power source (V.sub.DD) and ground. Each latch transistor is connected to a load device through a node or junction which is also connected to a capacitor. Between each capacitor and its junction are a pair of resistor elements such as depletion mode MOS devices.
U.S. Pat. No. 3,774,176 granted Nov. 20, 1973 to Karl-Ulrich Stein et al is directed to a "Semiconductor Memory Having Single Transistor Storage Elements and a Flip-Flop circuit for the Evaluation and Regeneration of Information". More specifically, U.S. Pat. No. 3,774,176 discloses a dynamic semiconductor memory having a plurality of single transistor storage elements connected to a digit line and respective selection lines, an evaluation and regeneration circuit including a flip-flop having a pair of input/output points, each of the points connected to one of the digit lines, and means connecting the points including a controllable semiconductor switch operable to place the points at equal potentials prior to reading from a selected storage element.
The IBM Technical Disclosure Bulletin publication entitled "Read-Only Storage Bit Precharge/Sense Circuit" by William Cordaro, Vol. 17, No. 4, Sept. 1974, page 1044 describes a read-only storage (ROS) sense circuit which is fabricated from N-channel and P-channel field effect transistors and supplies its own precharge current.
The IBM Technical Disclosure Bulletin publication entitled "Complementary FET Differential Amplifier" by William Cordaro, Vol. 16, No. 10, Mar. 1974, page 3227 describes a differential amplifier which is fabricated from N-channel and P-channel field effect transistors, the gain of which is determined by the channel lengths and normalized transconductance.